A VLSI implementation of RSA and IDEA encryption engineBuldas, Ahto; Põldre, JüriProceedings [of the] 15th NORCHIP Conference, Tallinn, 10-11 November 19971997 / p. 281-288: ill

At-speed testing and test quality evaluation for high-performance pipelined systems Töökiirusel testimine ja testi kvaliteedi hindamine kõrgjõudlus-konveierarhitektuuriga süsteemideleGorev, Maksim2015 https://digi.lib.ttu.ee/i/?3953

Automatic test generation system for VLSIJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the First Electronic Circuits and Systems Conference : Bratislava, Slovakia, September 4-5, 19971997 / p. 255-258

CAD of CCD VLSIZaycev, S.N.; Kanunnikov, A.I.; Pugachev, A.A.; Shilin, V.A.Automation, simulation & measurement : ASM'91 : 3rd biennal conference, Tallinn, October 7-11, 1991. Section S / Tallinn Technical University1992 / p. 120-122: ill

Control intensive digital system synthesisTammemäe, Kalle1997 http://www.ester.ee/record=b1060033*est

DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGARiazati, Mohammad; Daneshtalab, Masoud; Sjodin, Mikael; Lisper, BjornICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, November 23-25, 2020, Virtual Conference : Proceedings2020 / 4 p https://doi.org/10.1109/ICECS49266.2020.9294881

Defect-oriented BIST quality analysisKruus, Helena; Ubar, Raimund-Johannes; Raik, JaanBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 153-156 : ill

Dependability improvements of NoC-based systems = Töökindluse parandamine kiipvõrkudel põhinevates süsteemidesNiazmand, Behrad2018 https://digi.lib.ttu.ee/i/?9879

Design obfuscation versus testFarahmandi, Farimah; Sinanoglu, Ozgur; Blanton, Ronald; Pagliarini, Samuel Nascimento2020 IEEE European Test Symposium (ETS) : ETS 2020, May 25 - 29, 2020, Tallinn, Estonia2020 / 10 p https://doi.org/10.1109/ETS48528.2020.9131590

Design space exploration and optimisation for NoC-based timing sensitive systemsTagel, Mihkel; Ellervee, Peeter; Jervan, GertBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 177-180 : ill

Digital test in WEB-based environmentIvask, Eero2006 https://www.ester.ee/record=b2158119*est

Fault diagnosis of VLSI devices using alternative graph representationUbar, Raimund-JohannesProceedings of the 8th Symposium on Microcomputer and Microprocessor Applications, Budapest, October 12-14, 1994. Vol. 11994 / p. 34-44

Functional test generation for finite state machinesUbar, Raimund-Johannes; Brik, Marina; Jutman, Artur; Raik, Jaan; Bengtsson, Tomas; Kumar, ShashiBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 205-208 : ill

Graph embedding in boolean hypercubeFomina, Jelena; Zakrevskij, ArkadijBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 131-134 : ill

High-level synthesis of control and memory intensive applications : thesis submitted to the Royal Institute of Technology in partial fulfillment of the requirements for the degree of Doctor of TechnologyEllervee, Peeter2000

Hybrid built-in self-test : methods and tools for analysis and optimization of BIST = Sisseehitatud hübriidne isetestimine : meetodid ja vahendid analüüsiks ning optimeerimiseksOrasson, Elmet2007 https://www.ester.ee/record=b2305436*est

Multi-level test generation and fault diagnosis for finite state machinesUbar, Raimund-Johannes; Brik, MarinaDependable computing : proceedings / EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 19961996 / p. 264-281: ill

Optimization of built-in self-test in digital systems = Sisseehitatud enesetestimise optimeerimine digitaalsüsteemidesKruus, Helena2011

Representing transparency conditions in test generation for VLSI by decision diagramsUbar, Raimund-JohannesProceedings of the First Electronic Circuits and Systems Conference : Bratislava, Slovakia, September 4-5, 19971997 / p. 213-216

Riistvara kirjeldamiskeel - VHDL : metoodiline materjalTammemäe, Kalle2003 http://www.ester.ee/record=b1605950*est

Riistvara kirjeldamiskeel VHDL : metoodiline materjalTammemäe, Kalle2002 http://www.ester.ee/record=b1605950*est

Runtime contention and bandwidth-aware adaptive routing selection strategies for networks-on-chipSamman, Faizal; Hollstein, Thomas; Glesner, ManfredIEEE transactions on parallel and distributed systems2013 / p. 1411-1421 : ill

System-level design of timing-sensitive network-on-chip based dependable systems = Kiipvõrkudel põhinevate ajakriitiliste ja töökindlate süsteemide kõrgtaseme disainTagel, Mihkel2012 https://www.ester.ee/record=b2778263*est

Проектирование контролепригодных дискретных систем : учебное пособиеUbar, Raimund-Johannes1988 https://www.ester.ee/record=b1225400*est