A scalable model based RTL framework zamiaCAD for static analysisTšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) : October 7-10, 2012 Santa Cruz, USA Dream Inn, Santa Cruz, USA : [proceedings]2012 / p. 171-176 : ill

Applications of the open source HW design framework zamiaCADTšepurov, Anton; Tihhomirov, Valentin; Saif Abrar, Syed; Jenihhin, Maksim; Raik, JaanDATE 2012 University Booth : Design Automation and Test in Europe : Dresden, Germany, March 12-16, 20122012 / 1 p

Assessment of diagnostic test for automated bug localizationTihhomirov, Valentin; Tšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATW2013 : 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013 : [proceedings]2013 / [6] p. : ill

Automated design error localization in RTL designsJenihhin, Maksim; Tšepurov, Anton; Tihhomirov, Valentin; Raik, Jaan; Hantson, Hanno; Ubar, Raimund-Johannes; Bartsch, Günter; Meza Escobar, Jorge Hernan; Wuttke, Heinz-DietrichIEEE design & test of computers2014 / p. 83-92 : ill http://dx.doi.org/10.1109/MDAT.2013.2271420

Diagnostic test generation for statistical bug localization using evolutionary computationGaudesi, Marco; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin; Ubar, Raimund-JohannesApplications of Evolutionary Computation : 17th European Conference, EvoApplications 2014, Granada, Spain, April 23-25, 2014 : revised selected papers2014 / p. 425-436 : ill

Environment for fault simulation acceleration on FPGAEllervee, Peeter; Raik, Jaan; Tihhomirov, ValentinBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 217-220 : ill

Evaluating fault emulation on FPGAEllervee, Peeter; Raik, Jaan; Tihhomirov, Valentin; Tammemäe, KalleField-Programmable Logic and Applications : 14th International Conference, FPL 2004 : Antwerp, Belgium, August 30-September 1, 2004 : proceedings2004 / p. 354-363 : ill

Fast fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 20042004 / p. 35-40 https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=a6eb712498a5f23db3f95ad66bada257c21e96f0

Fault emulation on FPGA : a feasibility studyEllervee, Peeter; Raik, Jaan; Tihhomirov, ValentinIEEE NORCHIP 2003 : 21 Norchip Conference : Riga, Latvia, 10-11 November 2003 : proceedings2003 / p. 92-95 : ill

FPGA based fault emulation of synchronous sequential circuitsEllervee, Peeter; Raik, Jaan; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings [of] 22nd NORCHIP Conference : Oslo, Norway, 8-9 November 20042004 / p. 59-62 https://ieeexplore.ieee.org/abstract/document/1423822

Identification and rejuvenation of NBTI-critical logic paths in nanoscale circuitsJenihhin, Maksim; Squillero, Giovanni; Tihhomirov, Valentin; Kostin, Sergei; Raik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2016 / p. 273-289 : ill http://dx.doi.org/10.1007/s10836-016-5589-x

Improved fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 72-78 : ill

Localization of bugs in processor designs using zamiaCAD frameworkTšepurov, Anton; Tihhomirov, Valentin; Jenihhin, Maksim; Raik, Jaan13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions : Austin, USA, December 10–12, 20122012 / p. 1-6

PSL assertion checkers synthesis with ASM based HLS tool ABELITEJenihhin, Maksim; Baranov, Samary; Raik, Jaan; Tihhomirov, ValentinLATW 2012 : 13th IEEE Latin-American Test Workshop proceedings : April 10th-13th, 2012, Quito, Ecuador2012 / [6 p.] : ill https://ieeexplore.ieee.org/document/6261251

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPGPalermo, N.; Tihhomirov, Valentin; Copetti, Thiago; Jenihhin, Maksim; Raik, Jaan; Kostin, Sergei2015 16th Latin American Test Symposium (LATS 2015) : Puerto Vallarta, Mexico, 25-27 March 20152015 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2015.7102405

Rejuvenation of NBTI-impacted processors using evolutionary generation of assembler programsPellerey, Francesco; Jenihhin, Maksim; Squillero, Giovanni; Raik, Jaan; Sonza Reorda, Matteo; Tihhomirov, Valentin; Ubar, Raimund-Johannes2016 IEEE 25th Asian Test Symposium : 21-24 November 2016, Hiroshima, Japan2016 / p. 304-309 : ill https://doi.org/10.1109/ATS.2016.57

zamiaCAD : understand, develop and debug hardware designsJenihhin, Maksim; Tihhomirov, Valentin; Saif Abrar, Syed; Raik, Jaan; Bartsch, GünterDUHDe : 1st Workshop on Design Automation for Understanding Hardware Designs : March 28, 2014 : Friday Workshop at DATE 2014, Dresden, Germany2014 / p. 1-6

Using simulation statistics for bug localization in RTL designsTihhomirov, Valentin; Jenihhin, Maksim; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK seitsmenda aastakonverentsi artiklite kogumik : 15.-16. novembril 2013, Haapsalu2013 / p. 107-110 : ill

VHDL design debug framework based on zamiaCADTihhomirov, Valentin; Tšepurov, Anton; Saif Abrar, Syed; Jenihhin, Maksim; Raik, JaanDATE 2013 : Design Automation and Test in Europe, March 18-22, 2013, Grenoble, France2013 / [1] p. : ill