Checking sequence design for FSMKeevallik, Andres; Kruus, Margus; Lensen, HarriProceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 19981998 / p. 325-330

Mixed-level deterministic-random test generation for digital systemsJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 19981998 / p. 335-340

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generationLeveugle, R.; Ubar, Raimund-JohannesProceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 19981998 / p. 353-358