Fault oriented test pattern generation for sequential circuits using genetic algorithmsIvask, Eero; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop2000 / p. 319-320

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop2000 / p. 151-156 https://ieeexplore.ieee.org/document/873781