Diagnostic modeling of digital systems with multi-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, MaksimDesign and test technology for dependable systems-on-chip2011 / p. 92-118 : ill

High-level decision diagram simulation for diagnosis and soft-error analysisRaik, Jaan; Repinski, Urmas; Jenihhin, Maksim; Chepurov, AntonDesign and test technology for dependable systems-on-chip2011 / p. 294-309 : ill

High-speed logic level fault simulationUbar, Raimund-Johannes; Devadze, SergeiDesign and test technology for dependable systems-on-chip2011 / p. 310-335 : ill

PrefaceUbar, Raimund-Johannes; Raik, Jaan; Vierhaus, Heinrich TheodorDesign and test technology for dependable systems-on-chip2011 / p. xxii-xxviii

Sequential test set compaction in LFSR reseedingJutman, Artur; Aleksejev, Igor; Raik, JaanDesign and test technology for dependable systems-on-chip2011 / p. 476-493 : ill

System-level design of NoC-based dependable embedded systemsTagel, Mihkel; Ellervee, Peeter; Jervan, GertDesign and test technology for dependable systems-on-chip2011 / p. 1-36 : ill