• Hierarchical temporal memory implementation on FPGA using LFSR based spatial poolerKerner, Madis; Tammemäe, KalleProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 92-95 https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553