• An iterative approach to test time minimization for parallel hybrid BIST architecturesUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, Z.System-on-Chip Conference 2004 : Bastad, Sweden2004 / p. ? https://www.ida.liu.se/labs/eslab/publications/pap/db/latw04.pdf