Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model
author
Ubar, Raimund-Johannes
Borrione, Dominique
statement of authorship
R.Ubar, D.Borrione
source
XI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings
location of publication
Los Alamitos
publisher
IEEE Computer Society
year of publication
1998
pages
p. 51-54
url
https://ieeexplore.ieee.org/document/715409
subject term
elektriahelad
testimine
rikked
diagnostika (tehnika)
otsustusdiagrammid
ISBN
0-8186-8704-5
notes
Bibl. 9 ref
language
inglise