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SynAssert: automated synthesis of CSCA leakage patterns into cost-effective security assertions

author
Azarpeyvand, Ali Azarpeyvand
Eslami, Mohammad
Jervan, Gert
Raik, Jaan
Ghasempouri, Tara
statement of authorship
Ali Azarpeyvand, Mohammad Eslami, Gert Jervan, Jaan Raik and Tara Ghasempouri
source
Proceedings of 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
location of publication
Piscataway, New Jersey
publisher
IEEE
year of publication
2025
pages
6 p. : ill
conference name, date
2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 6-9 July 2025
conference location
Kalamata, Greece
url
https://doi.org/10.1109/ISVLSI65124.2025.11130310
subject term
vahemälu
turvalisus
lekked
riistvara
arvutivõrgud
Scopus
Conference proceedings at Scopus
Article at Scopus
WOS
Article at WOS
category (general)
Engineering
Computer science
category (sub)
Engineering. Electrical and electronic engineering
Engineering. Control and systems engineering
Computer science. Hardware and architecture
keyword
Cache Side-Channel Attacks
leakage pattern
register-transfer level
security assertion
security verification
ISSN
2159-3469
2159-3477
ISBN
9798331534776
notes
Bibliogr.: 38 ref
scientific publication
teaduspublikatsioon
classifier
3.1
TalTech department
Department of Computer Systems
language
English
inglise
Azarpeyvand, A.A., Eslami, M., Jervan, G., Raik, J., Ghasempouri, T. SynAssert: automated synthesis of CSCA leakage patterns into cost-effective security assertions // Proceedings of 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Piscataway, New Jersey : IEEE, 2025. 6 p. : ill. https://doi.org/10.1109/ISVLSI65124.2025.11130310