Niazmand, B., Azad, S.P., Flich, J., Raik, J., Jervan G., Hollstein, T.

Logic-based implementation of fault-tolerant routing in 3D Network-on-Chips

author

Niazmand, Behrad

Azad, Siavoosh Payandeh

Flich, Jose

Raik, Jaan

Jervan, Gert

Hollstein, Thomas

statement of authorship

Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein

source

2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) : Nara, Japan, 31 August - 2 September 2016

location of publication

Piscataway

publisher

IEEE

year of publication

2016

pages

[8] p. : ill

conference name, date

10th IEEE/ACM International Symposium on Networks-on-Chip, 31 August-2 September, 2016

conference location

Nara, Japan

url

https://doi.org/10.1109/NOCS.2016.7579317

subject term

kiipvõrgud

rikked

tolerantsid

keyword

fault-tolerance

routing algorithm

reconfigurability

reliability

network-on-chip

ISBN

978-1-4673-9030-9

notes

Bibliogr.: 25 ref

TTÜ department

arvutitehnika instituut

language

inglise

Niazmand, B., Azad, S.P., Flich, J., Raik, J., Jervan G., Hollstein, T. Logic-based implementation of fault-tolerant routing in 3D Network-on-Chips // 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) : Nara, Japan, 31 August - 2 September 2016. Piscataway : IEEE, 2016. [8] p. : ill. https://doi.org/10.1109/NOCS.2016.7579317