print

Design obfuscation versus test

author
Farahmandi, Farimah
Sinanoglu, Ozgur
Blanton, Ronald
Pagliarini, Samuel Nascimento
statement of authorship
Farimah Farahmandi, Ozgur Sinanoglu, Ronald Blanton, Samuel Pagliarini
source
2020 IEEE European Test Symposium (ETS) : ETS 2020, May 25 - 29, 2020, Tallinn, Estonia
location of publication
Danvers
publisher
IEEE
year of publication
2020
pages
10 p
conference name, date
2020 IEEE European Test Symposium (ETS), 25-29 May 2020
conference location
Tallinn, Estonia
url
https://doi.org/10.1109/ETS48528.2020.9131590
subject term
digitaalintegraallülitused
testimine
VLSI-ahelad
raalprojekteerimine
keyword
logic locking
logic obfuscation
integrated circuit design
test
automatic test pattern generation
high level synthesis
ISBN
978-1-7281-4312-5
notes
Bibliogr.: 41 ref
scientific publication
teaduspublikatsioon
classifier
3.1
TTÜ department
arvutisüsteemide instituut
language
inglise
Uurimisrühm
Centre for hardware security
Farahmandi, F., Sinanoglu, O., Blanton, R., Pagliarini, S. Design obfuscation versus test // 2020 IEEE European Test Symposium (ETS) : ETS 2020, May 25 - 29, 2020, Tallinn, Estonia. Danvers : IEEE, 2020. 10 p. https://doi.org/10.1109/ETS48528.2020.9131590