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book article
SCAAT: Secure cache alternative address table for mitigating cache logical side-channel attacks
Shalabi, Ameer
;
Ghasempouri, Tara
;
Ellervee, Peeter
;
Raik, Jaan
2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia
2020
/
art, 20035366, p. 213−217
https://doi.org/10.1109/DSD51259.2020.00043
book article
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keyword
40
1.
cache memory
2.
cache
3.
cache attacks
4.
cache security
5.
cache storage
6.
cache vulnerability analysis
7.
instruction cache
8.
activation memory
9.
Digital Object Memory
10.
in-memory databases
11.
learning and memory
12.
long short term memory
13.
long short -term memory (LSTM)
14.
long short-term memory
15.
long short-term memory (LSTM)
16.
Long Short-Term Memory Networks (LSTMs)
17.
long-short term memory
18.
long-short-term memory (LSTM)
19.
material with memory
20.
memory
21.
memory architecture
22.
memory bottleneck
23.
memory effect
24.
memory efficiency
25.
memory interconnect test
26.
memory kernels
27.
memory management
28.
memory network
29.
memory overhead
30.
memory systems
31.
memory testing
32.
memory-induced resonance
33.
National memory
34.
non-volatile memory
35.
processing-in-memory
36.
random access memory
37.
relaxed memory
38.
shape memory alloy
39.
Shape memory alloys
40.
shape memory efect
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