Töökindla arvutusriistvara keskus (TARK)
TalTech prioriteetne teadussuund
Klassifikaator (Frascati)
Uurimisrühma juht
Uurimisrühma liige
Doktorant
Võtmesõna
arvutusriistvara projekteerimine
ressursside tõhus arvutus
funktsionaalne ohutus
süsteemi enesetervise teadlikkus
ennustav hooldus
sardsüsteemid
arukad autonoomsed süsteemid
Ülevaade
Uurimiskeskuse fookuses on adaptiivne kihtideülese töökindluse ja enesetervise teadlikkuse tehnoloogia homsete arukate autonoomsete süsteemide ja värkvõrgu jaoks Eestis ja Euroopas. Teadusrühm uurib küberfüüsikaliste süsteemide alusarvutusriistvara toetades nende süsteemide heterogeensust ja tehisintelligentsusel põhinevat autonoomsust. Keskuses loodud teadmised pakuvad inseneridele disainilahendusi ja kohapealset instrumentaariumi tööstuslike süsteemide tõrgete haldamiseks.Keskuse põhikompetentsid on:• arvutusriistvara projekteerimine: VHDL ja Verilog projektid; projekteerimise keskkonnad (Cadence, Siemens-Mentor, Synopsys); rakendusspetsiifilised arvutusplatvormid (Mehitamata õhusõidukid ehk droonid)• FPGA-põhilised lahendused ja metodoloogiad: FPGA süsteemkiibid (Zynq, CycloneV); Projekteerimise keskkonnad (Xilinx Vivado, Altera/Intel Quartus, Lattice Diamond)• Tarkvara ja sardtarkvara arendus: Paljasmetalli rakendused, buudilaadurid, Linux draiverid ja Userspace rakendused; Operatsioonisüsteemid Petalinux, Yocto, FreeRTOS ja tarkvaraarenduskomplektid (SDK, ELDK)• Kihtideülene töökindlus ning rikete haldus: masinõppepõhised lahendused; funktsionaalne ohutus (standard ISO26262)• Testi ja tõrkeotsingu instrumendid: JTAG/IJTAG põhised lahendused (standardid IEEE-1149.1, IEEE-1149.6, IEEE-1687)
Tähtsamad tulemused
Ahmadilivani, M. H.; Taheri, M.; Raik, J.; Daneshtalab, M.; Jenihhin, M. (2023). DeepVigor: VulnerabIlity Value Ranges and Factors for DNNs’ Reliability Assessment. In: 28th IEEE European Test Symposium (ETS), Venice, Italy, May 22-26, 2023. (1−6). IEEE. DOI: 10.1109/ETS56758.2023.10174133
Selg, H.; Jenihhin, M.; Ellervee, P.; Raik, J. (2023). ML-Based Online Design Error Localization for RISCV Implementations. IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS): Crete, Greece, 03-05 July 2023. IEEE, 1−7. DOI: 10.1109/IOLTS59296.2023.10224864
Seotud projektid
Uurimisrühma tegevusperiood
2023
2022
2021
2020
2019
Seotud struktuuriüksus
Teadusgrupiga seotud publikatsioonid
- Ahmed, F., Jenihhin, M. A survey on UAV computing platforms : a hardware reliability perspective // Sensors (2022) vol. 22, 16, art. 6286.
https://doi.org/10.3390/s22166286 - Gürsoy, C.C., Kraak, D., Ahmed, F., Taouil, M., Jenihhin, M., Hamdioui, S. On BTI aging rejuvenation in memory address decoders // 2022 IEEE 23rd Latin American Test Symposium, LATS 2022. Piscataway, NJ : IEEE, 2022. Code 184360.
https://doi.org/10.1109/LATS57337.2022.9936940 - Nosrati, N., Jenihhin, M., Navabi, Z. MLC: a machine learning based checker for soft error detection in embedded processors // Proceedings - 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design, IOLTS 2022. New York : IEEE, 2022. Code 183305.
https://doi.org/10.1109/IOLTS56730.2022.9897309 - Gazori, P., Rahbari, D., Nickray, M. Saving time and cost on the scheduling of fog-based IoT applications using deep reinforcement learning approach // Future generation computer systems (2020) vol. 110, p. 1098-1115.
https://doi.org/10.1016/j.future.2019.09.060 - Rahbari, D., Nickray, M. Task offloading in mobile fog computing by classification and regression tree // Peer-to-Peer networking and applications (2020) vol. 13, 1, p. 104−122.
https://doi.org/10.1007/s12083-019-00721-7 - Kuts, V., Cherezova, N., Sarkans, M., Otto, T. Digital Twin : industrial robot kinematic model integration to the virtual reality environment // Journal of machine engineering (2020) vol. 20, 2, p. 53–64.
https://doi.org/10.36897/jme/120182 - Selg, H., Jenihhin, M., Ellervee, P. Wafer-level die re-test success prediction using machine learning // 21st IEEE Latin-American Test Symposium (LATS) 2020 : proceedings. Danvers : IEEE, 2020. 5 p.
https://doi.org/10.1109/LATS49555.2020.9093672 - Rahbari, D. Analyzing meta-heuristic algorithms for task scheduling in a fog-based IoT application // Algorithms (2022) vol. 15, 11, art. 397.
https://doi.org/10.3390/a15110397 - Augusto da Silva, F., Bagbaba, A. C., Sartoni, S., Cantoro, R., Reorda, M. S., Hamdioui, S., Sauer, C. Determined-safe faults identification : a step towards ISO26262 hardware compliant designs // 2020 25th IEEE European Test Symposium (ETS). : IEEE, 2020. 6 p. : ill.
https://doi.org/10.1109/ETS48528.2020.9131568 - Balakrishnan, A., Lange, T., Glorieux, M., Alexandrescu, D., Jenihhin, M. Composing graph theory and deep neural networks to evaluate SEU type soft error effects // 9th Mediterranean Conference on Embedded Computing (MECO'2020), Budva, Montenegro, 8-11 June 2020. Danvers : IEEE, 2020.
https://doi.org/10.1109/MECO49872.2020.9134279 - Rahbari, D., Alam, M. M., Le Moullec, Y., Jenihhin, M. Fast and fair computation offloading management in a swarm of drones using a rating-based federated learning approach // IEEE Access (2021) vol. 9, p. 113832-113849.
https://doi.org/10.1109/ACCESS.2021.3104117 - Cardoso Medeiros, G., Gürsoy, C.C., Fieback, M., Jenihhin, M. et al. A DFT scheme to improve coverage of hard-to-detect faults in FinFET SRAMs // 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 9-13 March 2020, Grenoble, France : proceedings. : EDAA, 2020. p. 792-797.
https://doi.org/10.23919/DATE48585.2020.9116278 - Lange, T., Balakrishnan, A., Glorieux, M. et al. Machine learning clustering techniques for selective mitigation of critical design features // Proceedings : 2020 26th IEEE International Symposium on On-Line Testing and Robust System Design : IOLTS 2020, Napoli, Italy, July 13-16, 2020 : virtual edition. Danvers : IEEE, 2020. 7 p. : ill.
https://doi.org/10.1109/IOLTS50870.2020.9159751 - Silva, F. A., Bagbaba, A. C., Ruospo, A., Jenihhin, M. et al. Special session : AutoSoC - a suite of open-source automotive SoC benchmarks // 2020 IEEE 38th VLSI TEST SYMPOSIUM (VTS) - VTS 2020 : proceedings. Danvers : IEEE, 2020. 9 p. : ill.
https://doi.org/10.1109/VTS48691.2020.9107599 - Tarique, T. A., Ahmed, F., Jenihhin, M., Ali, L. Unsupervised recycled FPGA detection using symmetry analysis // 12th International Conference on Electrical and Computer Engineering : ICECE 2022. : IEEE, 2022. p. 437-440.
https://doi.org/10.1109/ICECE57408.2022.10088856 - Rahbari, D., Alam, M. M., Le Moullec, Y., Jenihhin, M. Edge-to-Fog collaborative computing in a swarm of drones // Advances in Model and Data Engineering in the Digitalization Era : MEDI 2021 International Workshops: DETECT, SIAS, CSMML, BIOC, HEDA, Tallinn, Estonia, June 21–23, 2021 : proceedings. Cham : Springer, 2021. p. 78–87. (Communications in computer and information science ; 1481).
https://doi.org/10.1007/978-3-030-87657-9_6 - Oyeniran, A.S., Ubar, R., Jenihhin, M., Raik, J. High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors // Journal of electronic testing : theory and applications (2020) vol. 36, p. 87-103.
https://doi.org/10.1007/s10836-020-05856-7 - Oyeniran, A.S., Ubar, R., Jenihhin, M., Raik, J. Implementation-independent functional test for transition delay faults in microprocessors // 2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia. Danvers : IEEE, 2020. p. 646-650.
https://doi.org/10.1109/DSD51259.2020.00105 - Lai, X., Jenihhin, M., Selimis, G. et al. Early RTL analysis for SCA vulnerability in fuzzy extractors of memory-based PUF enabled devices // arXiv.org (2020) arXiv:2008.08409v1, 6 p. : ill.
https://doi.org/10.48550/arXiv.2008.08409 https://arxiv.org/abs/2008.08409 - Jürimägi, L., Ubar, R., Jenihhin, M., Raik, J. Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs // Microprocessors and microsystems (2020) vol. 77, art. 103117, 12 p.
https://doi.org/10.1016/j.micpro.2020.103117 - Heidari Iman, M.R., Raik, J., Jenihhin, M., Jervan, G., Ghasempouri, T. A methodology for automated mining of compact and accurate assertion sets // 2021 IEEE Nordic Circuits and Systems Conference (NorCAS) : Oslo, Norway, October 26-27. : IEEE, 2021. 7 p. : ill.
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9599865 https://doi.org/10.1109/NorCAS53631.2021.9599865 - Isaka, Y., Shintani, M., Ahmed, F. Inoue, M. Systematic unsupervised recycled field-programmable gate array detection // IEEE transactions on device and materials reliability (2022) vol. 22, 2, 10 p. : ill.
https://doi.org/10.1109/TDMR.2022.3164788 - Bagbaba, A.C., Augusto da Silva, F., Sonza Reorda, M., Hamdioui, S., Jenihhin, M., Sauer, C. Automated identification of application-dependent safe faults in automotive systems-on-a-chips // Electronics (2022) vol. 11, 3, art. 319.
https://doi.org/10.3390/electronics11030319 - Balakrishnan, A., Medeiros, G.C., Gürsoy, C.C., Hamdioui, S., Jenihhin, M., Alexandrescu, D. Modeling soft-error reliability under variability // 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 6-8 Oct. 2021. : IEEE, 2021. p. 1-6.
https://doi.org/10.1109/DFT52944.2021.9568295 - Bagbaba, A.C., Jenihhin, M., Ubar, R., Sauer, C. Representing gate-level SET faults by multiple SEU faults on RT-level // 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 13-15 July 2020 : proceedings. Danvers : IEEE, 2020. art. 19889351, 6 p. : ill.
https://doi.org/10.1109/IOLTS50870.2020.9159715 - Oyeniran, A. S., Ademilua, T., Kruus, M., Ubar, R. Environment for innovative university research training in the field of digital test // 2021 30th Annual Conference of the European Association for Education in Electrical and Information Engineering (EAEEIE). : IEEE, 2021.
https://doi.org/10.1109/EAEEIE50507.2021.9531003 - Selg, H., Jenihhin, M., Ellervee, P. JÄNES : a NAS framework for ML-based EDA applications // IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. : IEEE, 2021.
https://doi.org/10.1109/DFT52944.2021.9568321 - Alexandrescu, D., Balakrishnan, A., Lange, T., Glorieux, M. Enabling cross-layer reliability and functional safety assessment through ML-based compact models // Proceedings : 2020 26th IEEE International Symposium on On-Line Testing and Robust System Design : IOLTS 2020, Napoli, Italy, July 13-16, 2020 : virtual edition. Danvers : IEEE, 2020. 6 p. : ill.
https://doi.org/10.1109/IOLTS50870.2020.9159750 - Lai, X., Lange, T., Balakrishnan, A., Alexandrescu, D., Jenihhin, M. On antagonism between side-channel security and soft-error reliability in BNN inference engines // IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). : IEEE, 2021. p. 1-6.
https://doi.org/10.1109/VLSI-SoC53125.2021.9606981 - Jenihhin, M., Hamdioui, S., Sonza Reorda, M., Raik J. et al. RESCUE: interdependent challenges of reliability, security and quality in nanoelectronic systems // 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 9-13 March 2020, Grenoble, France : proceedings. Danvers : EDAA, 2020. art. 19690741 , 6 p.
https://doi.org/10.23919/DATE48585.2020.9116558 - Cherezova, N., Mihhailov, D., Devadze, S., Jutman, A. HLS-based optimization of tau triggering algorithm for LHC: a case study // 2022 18th Biennial Baltic Electronics Conference (BEC). : IEEE, 2022. 6 p. : ill.
https://doi.org/10.1109/BEC56180.2022.9935599 - Oyeniran, A.S., Jenihhin, M., Raik, J., Ubar, R. High-level fault diagnosis in RISC processors with Implementation-Independent Functional Test // 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) : Nicosia, Cyprus : 04-06 July 2022. : IEEE, 2022. p. 32-37.
https://doi.org/10.1109/ISVLSI54635.2022.00019 - Balakrishnan, A., Alexandrescu, D., Jenihhin, M., Lange, T., Glorieux, M. Gate-level graph representation learning : a step towards the improved stuck-at faults analysis // Proceedings of the Twenty Second International Symposium on Quality Electronic Design (ISQED) : Santa Clara, USA, 7-9 April 2021. : IEEE, 2021. p. 24-30.
https://doi.org/10.1109/ISQED51717.2021.9424256 - Taheri, M., Sheikhpour, S., Mahani, A., Jenihhin, M. A novel fault-tolerant logic style with self-checking capability // Proceedings - 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design, IOLTS 2022. Piscataway, New Jersey : IEEE, 2022. art. 183305 : ill.
https://doi.org/10.1109/IOLTS56730.2022.9897818 - Jenihhin, M., Oyeniran, A. S., Raik, J., Ubar, R. Implementation-independent test generation for a large class of faults in RISC processor modules // 24th Euromicro Conference on Digital System Design (DSD). : IEEE, 2021.
https://doi.org/10.1109/DSD53832.2021.00090 - Oyeniran, A.S., Ubar, R., Jenihhin, M., Raik, J. On test generation for microprocessors for extended class of functional faults // VLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers. Cham : Springer Nature, 2020. p. 21-44.
https://doi.org/10.1007/978-3-030-53273-4 - Oyeniran, A. S., Ubar, R. High-level functional test generation for microprocessor modules // Proceedings of 26th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2019 : Rzeszów, Poland, June 27 - 29, 2019. Lodz : Lodz University of Technology, 2019. p. 356-361 : ill.
https://doi.org/10.23919/MIXDES.2019.8787131 - Jürimägi, L., Ubar, R. Algorithm for restructuring of structurally synthesized BDDs // 2019 IEEE 31st International Conference on Microelectronics : Niš, Serbia September 16th-18th, 2019 : proceedings. Danvers : IEEE, 2019. p. 239-242 : ill.
https://doi.org/10.1109/MIEL.2019.8889578 - Jürimägi, L., Ubar, R. Conditional fault collapsing in digital circuits with shared structurally synthesized BDDs [Online resource] // BEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 2018. : IEEE, 2018. 4 p. : ill.
https://doi.org/10.1109/BEC.2018.8600967 - Vain, J., Tsiopoulos, L., Kharchenko, V., Kaur, A., Jenihhin, M., Raik, J., Nõmm, S. Energy-efficient multi-fragment Markov model guided online model-based testing for MPSoC // Green IT Engineering: Social, Business and Industrial Applications. Cham : Springer Nature, 2019. p. 273-297. (Studies in systems, decision and control ; 171).
https://doi.org/10.1007/978-3-030-00253-4_12 - Azad, S.P., Oyeniran, A.S., Ubar, R. Replication-based deterministic testing of 2-dimensional arrays with highly interrelated cells // 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems : DDECS 2018 : Budapest, Hungary 25-27 April, 2018 : proceedings. Piscataway : IEEE, 2018. p. 21-26 : ill.
https://doi.org/10.1109/DDECS.2018.00011 - Damljanovic, A., Squillero, G., Gürsoy, C. C., Jenihhin, M. On NBTI-induced aging analysis in IEEE 1687 reconfigurable scan networks // VLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]. Piscataway : IEEE, 2019. p. 335-340 : ill.
https://doi.org/10.1109/VLSI-SoC.2019.8920313 - Eggersgluss, S., Hamdioui, S., Jutman, A., Michael, M.K., Raik, J. et al. IEEE European Test Symposium (ETS) // 2019 IEEE International Test Conference (ITC). [S.l.] : IEEE, 2019. 4 p.
https://doi.org/10.1109/ITC44170.2019.9000148 - Ubar, R., Oyeniran, A.S., Medaiyese, O. Minimization of the high-level fault model for microprocessor control parts [Online resource] // BEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 2018. : IEEE, 2018. 4 p.: ill.
https://doi.org/10.1109/BEC.2018.8600980 - Jürimägi, L., Ubar, R., Viies, V. Equivalent transformations of structurally synthesized BDDs and applications // 2019 8th Mediterranean Conference on Embedded Computing (MECO). [S.l.] : IEEE, 2019. 6 p. : ill.
https://doi.org/10.1109/MECO.2019.8760283 - Vain, J., Kaur, A., Tsiopoulus, L., Raik, J., Jenihhin, M. Multi-view modeling for MPSoC design aspects [Online resource] // BEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 2018. : IEEE, 2018. 4 p.: ill.
https://doi.org/10.1109/BEC.2018.8600986 - Bagbaba, A. C., Jenihhin, M., Raik, J., Sauer, C. Efficient fault injection based on dynamic HDL slicing technique // 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece. Piscataway : IEEE, 2019. p. 52-53 : ill.
https://doi.org/10.1109/IOLTS.2019.8854419 - Kõusaar, J., Ubar, R.-J., Kostin, S., Devadze, S., Raik, J. Parallel critical path tracing fault simulation in sequential circuits // Proceedings of 25th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS : MIXDES 2018 : Gdynia, Poland, June 21–23, 2018. Lodz : Lodz University of Technology, 2018. p. 305-310 : ill.
https://doi.org/10.23919/MIXDES.2018.8436880 - Odintsov, S. In-field detection of degradation on PCB assembly high-speed buses // IEEE AUTOTESTCON 2018 : National Harbor, September 17-20, 2018 : proceedings. Piscataway : IEEE, 2018. 6 p.: ill.
https://doi.org/10.1109/AUTEST.2018.8532547 - Ehrenberg, H., Odintsov, S., Devadze, S., Jutman, A., Aleksejev, I., Wenzel, T. Ways for board and system test to benefit from FPGA embedded instrumentation // 2019 IEEE AUTOTESTCON. [S.l.] : IEEE, 2019. 10 p : ill.
https://doi.org/10.1109/AUTOTESTCON43700.2019.8961057 - Ubar, R., Jürimägi, L., Jenihhin, M., Raik, J., Olugbenga, N.-L., Viies, V. Timing-critical path analysis with structurally synthesized BDDs // 2018 7th Mediterranean Conference on Embedded Computing (MECO). New York : IEEE, 2018. 6 p. : ill.
https://doi.org/10.1109/MECO.2018.8406051 - Vierhaus, H. T. Jenihhin, M., Sonza Reorda, M. RESCUE : cross-sectoral PhD training concept for interdependent reliability, security and quality // 2018 12th European Workshop on Microelectronics Education (EWME) : September 24–26, 2018. Danvers : IEEE, 2018. p. 45-50 : ill.
https://doi.org/10.1109/EWME.2018.8629465 - Jürimagi, L., Ubar, R., Jenihhin, M., Raik, J., Devadze, S., Kostin, S. Hierarchical timing-critical paths analysis in sequential circuits // 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain. : IEEE, 2018. 6 p. : ill.
https://doi.org/10.1109/PATMOS.2018.8464176 - Naqvi, S. R., Anjum, Z., Sawalha, L., Jenihhin, M. et al. An optimization framework for dynamic pipeline management in computing systems // Computers & electrical engineering (2019) vol. 78, p. 242-258 : ill.
https://doi.org/10.1016/j.compeleceng.2019.07.013 - Avramenko, S., Azad, S. P., Violante, M., Niazmand, B.,Raik, J., Jenihhin, M. Upgrading QoSinNoC : efficient routing for mixed-criticality applications and power analysis // Proceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy. : IEEE, 2018. p. 207-212 : ill.
https://doi.org/10.1109/VLSI-SoC.2018.8644866 - Oyeniran, A. S., Ubar, R., Jenihhin, M., Gürsoy, C. C., Raik, J. Mixed-level identification of fault redundancy in microprocessors // LATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile,
March 11th - 13th 2019. [S.l.] : IEEE, 2019. 6 p. : ill.
https://doi.org/10.1109/LATW.2019.8704591 - Damljanovic, A., Jutman, A., Portolan, M., Tšertov, A. et al. Simulation-based equivalence checking between IEEE 1687 ICL and RTL // 2019 IEEE International Test Conference (ITC). [S.l.] : IEEE, 2019. paper. 7.3, 8 p. : ill.
https://doi.org/10.1109/ITC44170.2019.9000181 - Ubar, R., Kostin, S., Jenihhin, M., Raik, J., Jürimägi, L. Fast identification of true critical paths in sequential circuits // Microelectronics reliability (2018) vol. 81, p. 252-261 : ill.
https://doi.org/10.1016/j.microrel.2017.11.027 - Odintsov, S., Bozzoli, L., De Sio, C., Sterpone, L., Jutman, A. A new FPGA-based detection method for spurious variations in PCBA power distribution network // 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Cluj-Napoca, Romania : proceedings. Danvers : IEEE, 2019. 6 p. : ill.
https://doi.org/10.1109/DDECS.2019.8724662 - Janson, K., Treudler, C.J., Hollstein, T., Raik, J., Jenihhin, M., Fey, G. Software-level TMR approach for on-board data processing in space applications // 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems : DDECS 2018 : Budapest, Hungary 25-27 April, 2018 : proceedings. Piscataway : IEEE, 2018. p. 147-152 : ill.
https://doi.org/10.1109/DDECS.2018.00033 - Yousefzadeh, S., Basharkhah, K., Raik, J., Jenihhin, M. et al. An Accelerator-based architecture utilizing an efficient memory link for modern computational requirements // 2019 IEEE East-West Design & Test Symposium (EWDTS). [S.l.] : IEEE, 2019. 6 p. : ill.
https://doi.org/10.1109/EWDTS.2019.8884481 - Augusto da Silva, F., Bagbaba, A. C., Hamdioui, S., Sauer, C. Efficient methodology for ISO26262 functional safety verification // 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 1-3 July 2019, Rhodes, Greece. : IEEE, 2019. p. 255-256.
https://doi.org/10.1109/IOLTS.2019.8854449 - Oyeniran, A. S., Ubar, R., Jenihhin, M., ; Gürsoy, C. C., Raik, J. High-level combined deterministic and pseudo-exhuastive test generation for RISC processors // 2019 IEEE European Test Symposium (ETS) : proceedings. Danvers : IEEE, 2019. 6 p. : ill.
https://doi.org/10.1109/ETS.2019.8791526 - Bagbaba, A. C., Jenihhin, M., Raik, J., Sauer, C. Accelerating transient fault injection campaigns by using Dynamic HDL Slicing // 2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore. Danvers : IEEE, 2019. 7 p. : ill.
https://doi.org/10.1109/NORCHIP.2019.8906932 - Ubar, R., Jürimägi, L., Oyeniran, A. S., Jenihhin, M. True path tracing in structurally synthesized BDDs for testability analysis of
digital circuits // Euromicro Conference on Digital System Design : DSD 2019 : 28 - 30 August 2019
Kallithea, Chalkidiki, Greece : proceedings. Danvers : IEEE, 2019. p. 492-499 : ill.
https://doi.org/10.1109/DSD.2019.00077 - Oyeniran, A.S., Azad, S.P., Ubar, R.-J. Combined pseudo-exhaustive and deterministic testing of array multipliers // 2018 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) : THETA 21st edition, 24th-26th May, Cluj-Napoca, Romania : proceedings. Romania : IEEE, 2018. 6 p. : ill.
https://doi.org/10.1109/AQTR.2018.8402708 - Aleksandrowicz, G., Arbel, E., Bloem, R., Devadze, S., Jenihhin, M., Jutman, A., Raik, J., Shibin, K. et al. Designing reliable cyber-physical systems // Languages, design methods, and tools for electronic system design : selected contributions from FDL 2016. Cham : Springer, 2018. p. 15-38 : ill. (Lecture notes in electrical engineering; 454).
https://doi.org/10.1007/978-3-319-62920-9_2 - Kraak, D.H.P, Gürsoy, C.C., Jenihhin, M., Raik, J. et al. Software-based mitigation for memory address decoder aging // LATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile, March 11th - 13th 2019. [S.l.] : IEEE, 2019. 6 p. : ill.
https://doi.org/10.1109/LATW.2019.8704595 - Balakrishnan, A., Lange, T., Glorieux, M., Alexandrescu, D., Jenihhin, M. The validation of graph model-based, gate level low-dimensional feature data for machine learning applications // 2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore. Danvers : IEEE, 2019. 7 p.
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