prindi

Hierarchical defect-oriented fault simulation for digital circuits

autor
Blyzniuk, M.
Cibakova, Tatiana
Gramatova, Elena
Kuzmicz, W.
Lobur, M.
Pleskacz, Witold A.
Raik, Jaan
Ubar, Raimund-Johannes
vastutusandmed
M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar
allikas
IEEE European Test Workshop
ilmumiskoht
Cascais
ilmumisaasta
2000
leheküljed
p. 151-156
leitav
https://ieeexplore.ieee.org/document/873781
märksõna
elektriahelad
defektid
simulatsioon
keel
inglise
Blyzniuk, M., Cibakova, T., Gramatova, E., Kuzmicz, W., Lobur, M., Pleskacz, W., Raik, J., Ubar, R. Hierarchical defect-oriented fault simulation for digital circuits // IEEE European Test Workshop. Cascais, 2000. p. 151-156. https://ieeexplore.ieee.org/document/873781