Automatic SoC level test path synthesis based on partial functional models
author
TÅ¡ertov, Anton
Ubar, Raimund-Johannes
Jutman, Artur
Devadze, Sergei
statement of authorship
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
source
2011 Asian Test Symposium (ATS) : New Delhi, India
location of publication
[S.l.]
year of publication
2011
pages
p. 532-538
conference name, date
2011 Asian Test Symposium (ATS)
conference location
New Delhi, India
url
https://ieeexplore.ieee.org/document/6114730
subject term
integraallülitused
automatiseerimine
testimine
otsused
keyword
processor-centric board test
test path synthesis
JTAG
decision diagrams
PCBA component modeling
ISSN
1081-7735
language
inglise