Extensible open-source framework for translating RTL VHDL IP cores to SystemC
statement of authorship
Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
source
Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic
location of publication
Piscataway
publisher
year of publication
pages
p. 112-115
conference name, date
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), April 8-10, 2013
conference location
Karlovy Vary, Czech Republic
ISBN
978-1-4673-6133-0
notes
Bibliogr.: 20 ref
TTÜ department
language
inglise
Saif Abrar, S., Jenihhin, M., Raik, J. Extensible open-source framework for translating RTL VHDL IP cores to SystemC // Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic. Piscataway : IEEE, 2013. p. 112-115.