An iterative approach to test time minimization for parallel hybrid BIST architectures
author
Ubar, Raimund-Johannes
Jenihhin, Maksim
Jervan, Gert
Peng, Z.
statement of authorship
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng
source
System-on-Chip Conference 2004 : Bastad, Sweden
location of publication
[S.l.]
publisher
SOCWARE
year of publication
2004
pages
p. ?
language
inglise