Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
author
Leveugle, R.
Ubar, Raimund-Johannes
statement of authorship
R.Leveugle, R.Ubar
source
Electron technology
journal volume number month
Vol. 32
year of publication
1999
pages
3, p. 282-287 : ill
conference name, date
5th International Conference MIXDES'98 "Mixed design of integrated circuits and systems", June 18-20, 1998
conference location
Lodz, Poland
subject term
otsustusdiagrammid
süntees
VHDL (programmeerimiskeel)
notes
Ajakiri sisaldab konverentsi "5th International Conference MIXDES'98 "Mixed design of integrated circuits and systems", Lodz, Poland, June 18-20, 1998" materjale
language
inglise