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High-speed logic level fault simulation

author
Ubar, Raimund-Johannes
Devadze, Sergei
statement of authorship
Raimund Ubar, Sergei Devadze
source
Design and test technology for dependable systems-on-chip
location of publication
Hershey
publisher
Information Science Reference
year of publication
2011
pages
p. 310-335 : ill
url
https://www.igi-global.com/chapter/high-speed-logic-level-fault/51407
subject term
rikked
simulatsioon
loogikaelemendid
ISBN
978-1-60960-212-3
notes
Bibliogr. p. 332-334
language
inglise
Ubar, R., Devadze, S. High-speed logic level fault simulation // Design and test technology for dependable systems-on-chip. Hershey : Information Science Reference, 2011. p. 310-335 : ill. https://www.igi-global.com/chapter/high-speed-logic-level-fault/51407