Min, M., Männama, V., Paavle, T. - TalTech Research Portal

Settling time minimization in PLL frequency synthesizers

author

Min, Mart

Männama, Vello

Paavle, Toivo

statement of authorship

Mart Min, Vello Männama and Toivo Paavle

source

ICCSC'02 : 1st IEEE International Conference on Circuits and Systems for Communications, 26-28 June, 2002, St.Petersburg, Russia : proceedings

location of publication

Saint-Petersburg

publisher

St.Petersburg State Polytechnic University

year of publication

2002

pages

p. 366-369 : ill

ISBN

5-7422-0260-1

notes

Bibliogr.: 8 ref

Min, M., Männama, V., Paavle, T. Settling time minimization in PLL frequency synthesizers // ICCSC'02 : 1st IEEE International Conference on Circuits and Systems for Communications, 26-28 June, 2002, St.Petersburg, Russia : proceedings. Saint-Petersburg : St.Petersburg State Polytechnic University, 2002. p. 366-369 : ill.