prindi

Settling time minimization in PLL frequency synthesizers

autor
Min, Mart
Männama, Vello
Paavle, Toivo
vastutusandmed
Mart Min, Vello Männama and Toivo Paavle
allikas
ICCSC'02 : 1st IEEE International Conference on Circuits and Systems for Communications, 26-28 June, 2002, St.Petersburg, Russia : proceedings
ilmumiskoht
Saint-Petersburg
kirjastus/väljaandja
St.Petersburg State Polytechnic University
ilmumisaasta
2002
leheküljed
p. 366-369 : ill
ISBN
5-7422-0260-1
märkused
Bibliogr.: 8 ref
Min, M., Männama, V., Paavle, T. Settling time minimization in PLL frequency synthesizers // ICCSC'02 : 1st IEEE International Conference on Circuits and Systems for Communications, 26-28 June, 2002, St.Petersburg, Russia : proceedings. Saint-Petersburg : St.Petersburg State Polytechnic University, 2002. p. 366-369 : ill.