Gate-level graph representation learning : a step towards the improved stuck-at faults analysis
statement of authorship
Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux
source
Proceedings of the Twenty Second International Symposium on Quality Electronic Design (ISQED) : Santa Clara, USA, 7-9 April 2021
publisher
year of publication
pages
p. 24-30
conference name, date
2021 22nd International Symposium on Quality Electronic Design (ISQED), 7-9 April 2021
conference location
Santa Clara, USA
subject term
keyword
Line Graph
Single Stuck-at Faults
ISSN
1948-3287
ISBN
978-1-7281-7641-3
notes
Bibliogr.: 31 ref
scientific publication
teaduspublikatsioon
classifier
TTÜ department
language
inglise
Balakrishnan, A., Alexandrescu, D., Jenihhin, M., Lange, T., Glorieux, M. Gate-level graph representation learning : a step towards the improved stuck-at faults analysis // Proceedings of the Twenty Second International Symposium on Quality Electronic Design (ISQED) : Santa Clara, USA, 7-9 April 2021. : IEEE, 2021. p. 24-30.