Gate-level graph representation learning : a step towards the improved stuck-at faults analysis
author
Balakrishnan, Aneesh
Alexandrescu, Dan
Jenihhin, Maksim
Lange, Thomas
Glorieux, Maximilien
statement of authorship
Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux
source
Proceedings of the Twenty Second International Symposium on Quality Electronic Design (ISQED) : Santa Clara, USA, 7-9 April 2021
publisher
IEEE
year of publication
2021
pages
p. 24-30
conference name, date
2021 22nd International Symposium on Quality Electronic Design (ISQED), 7-9 April 2021
conference location
Santa Clara, USA
url
https://doi.org/10.1109/ISQED51717.2021.9424256
subject term
tõrked
diagrammid
graafilised meetodid
analüüs
tehisintellekt
informaatika
keyword
GraphSAGE (Graph Based Neural Network)
Line Graph
Deep Neural Networks
Functional Failure Rate (FFR)
Fault Coverage
Single Stuck-at Faults
ISSN
1948-3287
ISBN
978-1-7281-7641-3
notes
Bibliogr.: 31 ref
scientific publication
teaduspublikatsioon
classifier
3.1
TalTech department
arvutisüsteemide instituut
language
inglise
Reserch Group
Centre for trustworthy and efficient computing hardware (TECH)
Centre of dependable computing systems