print

The validation of graph model-based, gate level low-dimensional feature data for machine learning applications

author
Balakrishnan, Aneesh
Lange, Thomas
Glorieux, Maximilien
Alexandrescu, Dan
Jenihhin, Maksim
statement of authorship
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
source
2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore
location of publication
Danvers
publisher
IEEE
year of publication
2019
pages
7 p
conference name, date
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019
conference location
Helsinki, Finland
url
https://doi.org/10.1109/NORCHIP.2019.8906974
subject term
graafilised kasutajaliidesed
tehisõpe
tehisintellekt
mudelipõhine tarkvaraarendus
keyword
probabilistic graphical models
deep learning
machine learning (ML)
functional derating
Single-Event Upset (SEU)
gate-level netlist
Graph Modeling Language (GML)
ISBN
978-1-7281-2769-9
notes
Bibliogr.: 11 ref
TTÜ department
arvutisüsteemide instituut
language
inglise
Uurimisrühm
Centre for trustworthy and efficient computing hardware (TECH)
Centre of dependable computing systems
Balakrishnan, A., Lange, T., Glorieux, M., Alexandrescu, D., Jenihhin, M. The validation of graph model-based, gate level low-dimensional feature data for machine learning applications // 2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore. Danvers : IEEE, 2019. 7 p. https://doi.org/10.1109/NORCHIP.2019.8906974