Searching - TalTech Research Portal

Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles

Research Groups

Help and information

Searching

gate-level netlist (keyword)

—

—

—

—

Add criteria Advanced search filter

Clear

types of item

book ..

journal article ..

newspaper article ..

book article ..

dissertation ..

Open Access ..

Scientific publication ..

year

year of publication

Loading..

Loading..

TTÜ department

Loading..

Loading..

Loading..

name of the person

Loading..

Loading..

Clear

Number of records 3
Look more.. (1/21)
Export

export all inquiry results (3)
Save TXT fail

Save PDF fail

print
Open for editing with marked entries my bookmarks

display

sort
1

book article

Modeling gate-level abstraction hierarchy using graph convolutional neural networks to predict functional de-rating factorsBalakrishnan, Aneesh; Lange, Thomas; Glorieux, Maximilien; Alexandrescu, Dan; Jenihhin, Maksim2019 NASA/ESA conference on adaptive hardware and systems AHS 2019 : proceedings2019 / p. 72-78 : ill https://doi.org/10.1109/AHS.2019.00007

book article
Seotud publikatsioonid 1
- A synthetic, hierarchical approach for modelling and managing complex systems' quality and reliability = Sünteetiline, hierarhiline lähenemine keerukate süsteemide kvaliteedi ja töökindluse modelleerimiseks ja haldamiseks
2

book article

On the estimation of complex circuits functional failure rate by machine learning techniquesLange, Thomas; Balakrishnan, Aneesh; Glorieux, Maximilien; Alexandrescu, Dan; Sterpone, Luca49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks - DSN 2019 : Supplemental Volume : proceedings2019 / p. 35-41 : ill https://doi.org/10.1109/DSN-S.2019.00021

book article
Seotud publikatsioonid 1
- A synthetic, hierarchical approach for modelling and managing complex systems' quality and reliability = Sünteetiline, hierarhiline lähenemine keerukate süsteemide kvaliteedi ja töökindluse modelleerimiseks ja haldamiseks
3

book article

The validation of graph model-based, gate level low-dimensional feature data for machine learning applicationsBalakrishnan, Aneesh; Lange, Thomas; Glorieux, Maximilien; Alexandrescu, Dan; Jenihhin, Maksim2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore2019 / 7 p https://doi.org/10.1109/NORCHIP.2019.8906974

book article
Seotud publikatsioonid 1
- A synthetic, hierarchical approach for modelling and managing complex systems' quality and reliability = Sünteetiline, hierarhiline lähenemine keerukate süsteemide kvaliteedi ja töökindluse modelleerimiseks ja haldamiseks

Number of records 3, displaying 1 - 3

1. gate-level netlist
2. gate-level analysis
3. gate-level circuit abstraction
4. register transfer and gate level simulation
5. logic level and high level BDDs
6. Field Programmable Gate Array (FPGA)
7. field programmable gate arrays
8. field-programmable gate array
9. Field-Programmable Gate Array (FPGA)
10. field-programmable gate arrays
11. FPGA (field-programmable gate array)
12. GaTe
13. gate and register transfer levels
14. gate delay
15. gate driver
16. Gate Injection Transistor (GIT)
17. Golden gate assembly
18. insulated gate bipolar transistors
19. insulated gate-commutated thyristors
20. NBTI-critical gate
21. Opal Kelly ﬁeld programmable gate array (FPGA)

vaste

sort

Otsing
Valikud 0

year of publication

author

TTÜ department

subject term

series

name of the person

keyword

TalTech Library

Akadeemia tee 1

13519

TalTech homepage TalTech Library homepage Digikogu Digiteek Repository

6203551

data@taltech.ee

TalTech Raamatukogu