Exploiting high-level descriptions for circuits fault tolerance assessments
author
Benso, A.
Prinetto, Paolo
Rebaudengo, M.
Sonza Reorda, Matteo
Raik, Jaan
Ubar, Raimund-Johannes
statement of authorship
A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar
source
1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, October 20-22, 1997
location of publication
[S.l.]
publisher
IEEE
year of publication
1997
pages
p. 212-216
url
https://ieeexplore.ieee.org/document/628327
subject term
elektriahelad
rikked
avastamine
modelleerimine (teadus)
simulatsioon
language
inglise