FSMD RTL design manipulation for clock interface abstraction
statement of authorship
Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
source
2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 10-13 August 2015, Kerala, India
location of publication
[S.l.]
publisher
year of publication
pages
p. 463-468 : ill
conference name, date
2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 10-13 August, 2015
conference location
Kerala, India
ISBN
978-1-4799-8790-0
notes
Bibliogr.: 22 ref
TTÜ department
language
inglise
subject term
keyword
Register Transfer Level - RTL
Algorithmic State Machine - ASM
Finite State Machine - FSM
Abrar, S.S., Jenihhin, M., Raik, J. FSMD RTL design manipulation for clock interface abstraction // 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 10-13 August 2015, Kerala, India. [S.l.] : IEEE, 2015. p. 463-468 : ill.