Avramenko, S., Azad, S. P., Violante, M., Niazmand, B.,Raik, J., Jenihhin, M.

full record print

Upgrading QoSinNoC : efficient routing for mixed-criticality applications and power analysis

author

Avramenko, Serhiy

Azad, Siavoosh Payandeh

Violante, Massimo

Niazmand, Behrad

Raik, Jaan

Jenihhin, Maksim

statement of authorship

Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin

source

Proceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy

publisher

IEEE

year of publication

2018

pages

p. 207-212 : ill

conference name, date

IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 8-10, 2018

conference location

Verona, Italy

url

https://doi.org/10.1109/VLSI-SoC.2018.8644866

ISSN

2324-8440

2324-8432

ISBN

978-1-5386-4756-1

978-1-5386-4757-8

notes

Bibliogr.: 18 ref

TTÜ department

arvutisüsteemide instituut

language

inglise

Märksõnad ja võtmesõnad

subject term

kiipvõrgud

kvaliteet

keyword

mixed-criticality

network-on-chip

quality-of-service

Reserch Group

Centre for trustworthy and efficient computing hardware (TECH)

Centre of dependable computing systems

Avramenko, S., Azad, S. P., Violante, M., Niazmand, B.,Raik, J., Jenihhin, M. Upgrading QoSinNoC : efficient routing for mixed-criticality applications and power analysis // Proceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy. : IEEE, 2018. p. 207-212 : ill. https://doi.org/10.1109/VLSI-SoC.2018.8644866