full record print

The validation of graph model-based, gate level low-dimensional feature data for machine learning applications

author
statement of authorship
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
source
location of publication
Danvers
publisher
year of publication
pages
7 p
conference name, date
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019
conference location
Helsinki, Finland
url
ISBN
978-1-7281-2769-9
notes
Bibliogr.: 11 ref
TTÜ department
language
inglise
Reserch Group
Centre for trustworthy and efficient computing hardware (TECH)
Centre of dependable computing systems
Balakrishnan, A., Lange, T., Glorieux, M., Alexandrescu, D., Jenihhin, M. The validation of graph model-based, gate level low-dimensional feature data for machine learning applications // 2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore. Danvers : IEEE, 2019. 7 p. https://doi.org/10.1109/NORCHIP.2019.8906974