Jenihhin, M., Oyeniran, A. S., Raik, J., Ubar, R.

full record print

Implementation-independent test generation for a large class of faults in RISC processor modules

author

Jenihhin, Maksim

Oyeniran, Adeboye Stephen

Raik, Jaan

Ubar, Raimund-Johannes

statement of authorship

Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar

source

24th Euromicro Conference on Digital System Design (DSD)

publisher

IEEE

year of publication

2021

conference name, date

24th Euromicro Conference on Digital System Design (DSD), 01-03 September 2021

conference location

Palermo, Italy

url

https://doi.org/10.1109/DSD53832.2021.00090

ISBN

978-1-6654-2703-6

scientific publication

teaduspublikatsioon

TTÜ department

arvutisüsteemide instituut

language

inglise

Märksõnad ja võtmesõnad

subject term

protsessorid

rikked

riistvara

keyword

RISC processors

implementation-independent test generation

high-level functional fault model

Teaduspublikatsiooni meetrika

classifier

3.1

Reserch Group

Centre for trustworthy and efficient computing hardware (TECH)

Centre of dependable computing systems

Jenihhin, M., Oyeniran, A. S., Raik, J., Ubar, R. Implementation-independent test generation for a large class of faults in RISC processor modules // 24th Euromicro Conference on Digital System Design (DSD). : IEEE, 2021. https://doi.org/10.1109/DSD53832.2021.00090