print

Verifying cache architecture vulnerabilities using a formal security verification flow

author
Ghasempouri, Tara
Raik, Jaan
Paul, Kolin
Reinbrecht, Cezar
Hamdioui, Said
Taouil, Mottaqiallah
statement of authorship
Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah ‪Taouil‬
source
Microelectronics reliability
publisher
Elsevier
journal volume number month
vol. 119
year of publication
2021
pages
art. 114085
url
https://doi.org/10.1016/j.microrel.2021.114085
subject term
turvaelemendid
rünnakud
informaatika
keyword
side-channel attacks
security verification
cache attacks
cache security
formal verification
ISSN
0026-2714
notes
Bibliogr.: 65 ref
scientific publication
teaduspublikatsioon
classifier
1.1
Scopus
Journal metrics at Scopus
Article at Scopus
WOS
Journal metrics at WOS
Article at WOS
category (general)
Engineering
Physics and astronomy
Materials science
category (sub)
Engineering. Safety, risk, reliability and quality
Engineering. Electrical and electronic engineering
Physics and astronomy. Condensed matter physics
Materials science. Surfaces, coatings and films
Physics and astronomy. Atomic and molecular physics, and optics
Materials science. Electronic, optical and magnetic materials
kvartiil
Q2
TTÜ department
arvutisüsteemide instituut
language
inglise
Uurimisrühm
Centre of dependable computing systems
Ghasempouri, T., Raik, J., Paul, K., Reinbrecht, C., Hamdioui, S., ‪Taouil‬, M. Verifying cache architecture vulnerabilities using a formal security verification flow // Microelectronics reliability (2021) vol. 119, art. 114085. https://doi.org/10.1016/j.microrel.2021.114085