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Automated minimization of concurrent online checkers for network-on-chipsSaltarelli, Pietro; Niazmand, Behrad; Hariharan, Ranganathan; Raik, Jaan; Jervan, Gert; Hollstein, Thomas10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip (ReCoSoC 2015) : Bremen, 29 June - 1 July 20152015 / [8] p. : ill http://dx.doi.org/10.1109/ReCoSoC.2015.7238079

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dissertation

Cost-effective concurrent hardware checkers for network on chip based system on chip = Kulutõhusad süsteemiga paralleelsed rikkemonitorid kiipvõrkudel põhinevatele kiipsüsteemideleHariharan, Ranganathan2019 https://digi.lib.ttu.ee/i/?12854 https://www.ester.ee/record=b5243161*est

dissertation

3

book article

Extended checkers for control part of routers in network-on-chipsHariharan, Ranganathan; Niazmand, Behrad; Hollstein, Thomas; Raik, Jaan; Jervan, GertMEDIAN 2015 : the 4th Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : March 13, 2015, Grenoble, France2015 / p. 36-39 : ill

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book article

Extended checkers for logic-based distributed routing in network-on-chipsNiazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, JaanProceedings of the 8th Annual Conference of the Estonian National Doctoral School in Information and Communication Technologies : December 5-6, 2014, Rakvere2014 / p. 83-86 : ill

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5

book article

Extended checkers for logic-based distributed routing in network-on-chipsNiazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, JaanBEC 2014 : 2014 14th Biennial Baltic Electronics Conference : proceedings of the 14th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 6-8, 2014, Tallinn, Estonia2014 / p. 77-80 : ill

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book article

A framework for area-efficient concurrent online checkers designSaltarelli, Pietro; Niazmand, Behrad; Hariharan, Ranganathan; Raik, Jaan; Jervan, Gert; Hollstein, ThomasMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 64-69 : ill

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book article

A framework for combining concurrent checking and online embedded test for low-latency fault detection in NoC routersSaltarelli, Pietro; Niazmand, Behrad; Raik, Jaan; Govind, Vineeth; Hollstein, Thomas; Jervan, Gert; Hariharan, RanganathanNOCS '15 : International Symposium on Networks-on-Chip : Vancouver, BC, Canada, September 28-30, 20152015 / [8] p. : ill http://dx.doi.org/10.1145/2786572.2788713

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8

book article

A framework for comprehensive automated evaluation of concurrent online checkersSaltarelli, Pietro; Niazmand, Behrad; Raik, Jaan; Hariharan, Ranganathan; Jervan, Gert; Hollstein, ThomasEuromicro Conference on Digital System Design : DSD 2015 : 26-28 August 2015, Funchal, Madeira, Portugal : proceedings2015 / p. 288-292 : ill http://dx.doi.org/10.1109/DSD.2015.15

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book article

From RTL liveness assertions to cost-effective hardware checkersHariharan, Ranganathan; Ghasempouri, Tara; Niazmand, Behrad; Raik, JaanXXXIII Conference on Design of Circuits and Integrated Systems (DCIS) : proceedings2018 / 6 p. : ill https://doi.org/10.1109/DCIS.2018.8681487

book article

Hariharan, Ranganathan (author)

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