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Architectural solutions for high-speed data processing demands of CERN LHC detectors with FPGA and high-level synthesis (title)
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Architectural solutions for high-speed data processing demands of CERN LHC detectors with FPGA and high-level synthesis
Devadze, Sergei
;
Nielsen, Christine Elizabeth
;
Mihhailov, Dmitri
;
Ellervee, Peeter
2024 IEEE Nordic Circuits and Systems Conference (NorCAS)
2024
https://doi.org/10.1109/NorCAS64408.2024.10752490
Article at Scopus
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high level synthesis
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high-level decision diagrams (HLDD) synthesis
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high-level synthesis
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High-Level Synthesis (HLS)
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high-level synthesis for test
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high-level test data generation
7.
logic level and high level BDDs
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