IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 25-27 October 2000, Yamanashi, Japan : proceedings (source)

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  • book article
    Test cost minimization for hybrid BISTJervan, Gert; Peng, Zebo; Ubar, Raimund-JohannesIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 25-27 October 2000, Yamanashi, Japan : proceedings2000 / p. 283-298 : ill https://ieeexplore.ieee.org/abstract/document/887168
    book article
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