Test cost minimization for hybrid BIST
statement of authorship
Gert Jervan, Zebo Peng, Raimund Ubar
source
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 25-27 October 2000, Yamanashi, Japan : proceedings
location of publication
Los Alamitos, CA
publisher
year of publication
pages
p. 283-298 : ill
ISBN
0-7695-0719-0
notes
Bibliogr.: 8 ref
Jervan, G., Peng, Z., Ubar, R. Test cost minimization for hybrid BIST // IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 25-27 October 2000, Yamanashi, Japan : proceedings. Los Alamitos, CA : IEEE Computer Society, 2000. p. 283-298 : ill.