Blyzniuk, M., Cibakova, T., Gramatova, E., Kuzmicz, W., Lobur, M., Pleskacz, W., Raik, J., Ubar, R.

Hierarchical defect-oriented fault simulation for digital circuits

author

Blyzniuk, M.

Cibakova, Tatiana

Gramatova, Elena

Kuzmicz, W.

Lobur, M.

Pleskacz, Witold A.

Raik, Jaan

Ubar, Raimund-Johannes

statement of authorship

M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar

source

IEEE European Test Workshop

location of publication

Cascais

year of publication

2000

pages

p. 151-156

url

https://ieeexplore.ieee.org/document/873781

subject term

elektriahelad

defektid

simulatsioon

language

inglise

Blyzniuk, M., Cibakova, T., Gramatova, E., Kuzmicz, W., Lobur, M., Pleskacz, W., Raik, J., Ubar, R. Hierarchical defect-oriented fault simulation for digital circuits // IEEE European Test Workshop. Cascais, 2000. p. 151-156. https://ieeexplore.ieee.org/document/873781