Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler
author
statement of authorship
Madis Kerner and Kalle Tammemae
location of publication
Piscataway
publisher
year of publication
pages
p. 92-95
conference name, date
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 19-21, 2017
conference location
Dresden, Germany
ISSN
2473-2117
ISBN
978-1-5386-0471-7
notes
Bibliogr.: 12 ref
TTÜ department
language
inglise
Kerner, M. Tammemäe, K. Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler // Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany. Piscataway : IEEE, 2017. p. 92-95.