Correct reuse of complex design units during high level synthesis : verification issues
autor
vastutusandmed
J. Dushina, ... [et al.]
allikas
IEEE International High Level Design Validation and Test Workshop, Oakland, California, USA, November 15-16, 1996 : proceedings
ilmumiskoht
[S.l.]
ilmumisaasta
keel
inglise
Dušina, J. et al. Correct reuse of complex design units during high level synthesis : verification issues // IEEE International High Level Design Validation and Test Workshop, Oakland, California, USA, November 15-16, 1996 : proceedings. [S.l.], 1996.