Fault simulation and code coverage analysis of RTL designs using high-level decision diagrams = Rikete simuleerimine ja koodikatte analüüs register-siirde tasemel kasutades kõrgtaseme otsustusdiagramme
author
supervisor
statement of authorship
Uljana Reinsalu ; [supervisors: Peeter Ellervee, Jaan Raik, Aleksander Sudnitsõn]
type of dissertation
doktoritöö
university/scientific institution
Tallinna Tehnikaülikool
location of publication
Tallinn
publisher
year of publication
pages
145 p. : ill
series
Theses of Tallinn University of Technology. C, Thesis on informatics and system engineering, ISSN 1406-4731 ; 86
subject term
subject of form
ISSN
1406-4731
ISBN
978-9949-23-476-9
978-9949-23-477-6 (pdf)
notes
Includes bibliogr
Thesis (Ph.D. in Computer and Systems Engineering) : Tallinn University of Technology, 2013
Autori CV inglise ja eesti keeles, lk. 137-140
Ka eestikeelse tiitellehega
Kokkuvõte eesti keeles, lk. 9
TTÜ department
language
inglise
Reinsalu, U. Fault simulation and code coverage analysis of RTL designs using high-level decision diagrams = Rikete simuleerimine ja koodikatte analüüs register-siirde tasemel kasutades kõrgtaseme otsustusdiagramme. Tallinn : TUT Press, 2013. 145 p. : ill. (Theses of Tallinn University of Technology. C, Thesis on informatics and system engineering, ISSN 1406-4731 ; 86).