Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model
vastutusandmed
R.Ubar, D.Borrione
ilmumiskoht
Los Alamitos
kirjastus/väljaandja
ilmumisaasta
leheküljed
p. 51-54
ISBN
0-8186-8704-5
märkused
Bibl. 9 ref
Ubar, R., Borrione, D. Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model // XI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings. Los Alamitos : IEEE Computer Society, 1998. p. 51-54.