A hybrid BIST architecture and its optimization for SoC testing
statement of authorship
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
source
Proceedings of the 3rd International Symposium on Quality Electronic Design : ISQED 2002, March 18-21, 2002, San Jose, California
location of publication
Washington
publisher
year of publication
pages
p. 273-279 : ill
ISBN
0-7695-1561-4
notes
Bibliogr.: 15 ref
Jervan, G., Peng, Z., Ubar, R.-J., Kruus, H. A hybrid BIST architecture and its optimization for SoC testing // Proceedings of the 3rd International Symposium on Quality Electronic Design : ISQED 2002, March 18-21, 2002, San Jose, California. Washington : IEEE Computer Society, 2002. p. 273-279 : ill.