An iterative approach to test time minimization for parallel hybrid BIST architectures
statement of authorship
R. Ubar, M. Jenihhin, G. Jervan, Z. Peng
source
System-on-Chip Conference 2004 : Bastad, Sweden
location of publication
[S.l.]
publisher
SOCWARE
year of publication
pages
p. ?
language
inglise
Ubar, R.-J., Jenihhin, M., Jervan, G., Peng, Z. An iterative approach to test time minimization for parallel hybrid BIST architectures // System-on-Chip Conference 2004 : Bastad, Sweden. [S.l.] : SOCWARE, 2004. p. ?.