Hybrid BIST energy minimisation technique for system-on-chip testing
statement of authorship
G.Jervan, Z.Peng, T.Shchenova and R.Ubar
source
IEE proceedings computers & digital techniques
journal volume number month
Vol. 153
year of publication
pages
4, p. 208-216 : ill
subject term
ISSN
1350-2387
notes
Bibliogr.: 37 ref
language
inglise
Jervan, G., Peng, Z., Shchenova, T., Ubar, R.-J. Hybrid BIST energy minimisation technique for system-on-chip testing // IEE proceedings computers & digital techniques (2006) Vol. 153, 4, p. 208-216 : ill.