Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems
statement of authorship
Valery Sklyarov, Iouliia Skliarova, Artjom Rjabov, and Alexander Sudnitson
publisher
journal volume number month
vol. 66, 3
year of publication
pages
p. 323-335 : ill
subject term
keyword
parallel data processing
iterative networks
communication-time processing
Field-Programmable Gate Array (FPGA)
Peripheral Component Interconnect (PCI) express bus
ISSN
1736-6046
notes
Bibliogr.: 26 ref
Kokkuvõte: Kiired iteratiivsed ahelad ja RAM-i baasil ühendajad, kiirendamaks andmete sortimist riist- ning tarkvara süsteemides
Open Access
Open Access
scientific publication
teaduspublikatsioon
classifier
category (general)
category (sub)
kvartiil
TTÜ department
language
inglise
Sklyarov, V., Skliarova, I., Rjabov, A., Sudnitsõn, A. Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems // Proceedings of the Estonian Academy of Sciences (2017) vol. 66, 3, p. 323-335 : ill.