Comprehensive performance and robustness analysis of 2D turn models for network-on-chips
author
statement of authorship
Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein
source
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
location of publication
Piscataway
publisher
year of publication
pages
p. 1476-1479 : ill
conference name, date
50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, 28.-31. May, 2017
conference location
Baltimore, United States
ISSN
2379-447X
0271-4310
ISBN
978-1-4673-6852-0
notes
bibliogr.: 13 ref
scientific publication
teaduspublikatsioon
TTÜ department
language
inglise
subject term
keyword
WOS
kvartiil
classifier
category (general)
category (sub)
Azad, S.P., Niazmand, B., Janson, K., Raik, J., Jervan, G., Hollstein, T. et al. Comprehensive performance and robustness analysis of 2D turn models for network-on-chips // 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway : IEEE, 2017. p. 1476-1479 : ill.