High-speed logic level fault simulation
statement of authorship
Raimund Ubar, Sergei Devadze
location of publication
Hershey
publisher
year of publication
pages
p. 310-335 : ill
ISBN
978-1-60960-212-3
notes
Bibliogr. p. 332-334
language
inglise
Ubar, R., Devadze, S. High-speed logic level fault simulation // Design and test technology for dependable systems-on-chip. Hershey : Information Science Reference, 2011. p. 310-335 : ill.