Fault model and test synthesis for RISC-processors
statement of authorship
R.Ubar, A.Markus, G.Jervan, J.Raik
location of publication
[Tallinn]
year of publication
pages
p. 229-232: ill
ISBN
9985-59-026-0
notes
Bibl. 6 ref
Ubar, R., Markus, A., Jervan, G., Raik, J. Fault model and test synthesis for RISC-processors // BEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings. [Tallinn], 1996. p. 229-232: ill.