Azad, S.P., Niazmand, B., Janson, K., Raik, J., Jervan, G., Hollstein, T. et al.

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

author

Azad, Siavoosh Payandeh

Niazmand, Behrad

Janson, Karl

Kogge, Thilo

Raik, Jaan

Jervan, Gert

Hollstein, Thomas

statement of authorship

Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein

source

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

location of publication

Piscataway

publisher

IEEE

year of publication

2017

pages

p. 1476-1479 : ill

conference name, date

50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, 28.-31. May, 2017

conference location

Baltimore, United States

url

https://doi.org/10.1109/ISCAS.2017.8050634

subject term

kiipvõrgud

marsruutimine

algoritmid

keyword

turn model

routing algorithm

robustness

minimal path

network-on-chip

ISSN

2379-447X

ISBN

978-1-4673-6852-0

notes

bibliogr.: 13 ref

TTÜ department

arvutisüsteemide instituut

language

inglise

Azad, S.P., Niazmand, B., Janson, K., Raik, J., Jervan, G., Hollstein, T. et al. Comprehensive performance and robustness analysis of 2D turn models for network-on-chips // 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway : IEEE, 2017. p. 1476-1479 : ill. https://doi.org/10.1109/ISCAS.2017.8050634