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Defect-oriented test- and layout-generation for standard-cell ASIC designsSudbrock, Joachim; Raik, Jaan; Ubar, Raimund-Johannes; Kuzmicz, Wieslaw; Pleskacz, Witold A.Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 79-82 : ill https://ieeexplore.ieee.org/document/1559781

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Deterministic defect-oriented test generation for combinational circuitsRaik, Jaan; Ubar, Raimund-Johannes; Sudbrock, Joachim; Kuzmicz, Wieslaw; Pleskacz, Witold A.LATW 2005 : 6th IEEE Latin-American Test Workshop : March 30 - April 2, 2005, Salvador, Bahia, Brazil : [digest of papers]2005 / p. 325-330 : ill

book article

DOT: new deterministic defect-oriented ATPG toolRaik, Jaan; Ubar, Raimund-Johannes; Sudbrock, Joachim; Kuzmicz, Wieslaw; Pleskacz, Witold A.European Test Symposium : ETS 2005 : 22-25 May 2005, Tallinn, Estonia : proceedings2005 / p. 96-101 : ill

book article

Hierarchical analysis of short defects between metal lines in CMOS ICPleskacz, Witold A.; Jenihhin, Maksim; Raik, Jaan; Rakowski, Michal; Ubar, Raimund-Johannes; Kuzmicz, WieslawProceedings : 11th EUROMICRO Conference on Digital System Design : Architectures, Methods and Tools : (DSD 2008) : September 3-5, 2008, Parma, Italy2008 / p. 729-734 : ill https://ieeexplore.ieee.org/document/4669309

book article

Module level defect simulation in digital circuitsKuzmicz, Wieslaw; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering2001 / 4, p. 253-268

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