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Abstraction of clock interface for conversion of RTL VHDL to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, Jaan2014 IEEE International Advance Computing Conference (IACC) : February 21-22, 2014, Gurgaon, India2014 / p. 50-55 : ill

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Conversion error of exponential to second order polynomial ZIP load model conversionLeinakse, Madis; Kilter, Jako2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe), 12-15 June 2018 : conference proceedings2018 / p. 1-5 https://doi.org/10.1109/EEEIC.2018.8493667

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High-performance analogue measurement using internal enhanced PWM and ADC of a DSP-chipMärtens, Olev; Min, Mart; Trampärk, Harri; Liimets, AivarWISP2007 proceedings : 5th IEEE International Symposium on Intelligent Signal Processing : Alcala de Henares, Madrid (Spain), October 3-5, 20072007 / [5] p https://ieeexplore.ieee.org/document/4447593

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Влияние неидеальностей кос на качество преобразования импедансаSchiff, Gunnar; Kukk, VelloТруды по электротехнике и автоматике : сборник статей. 141976 / с. 3-10 : илл https://www.ester.ee/record=b2190768*est https://digikogu.taltech.ee/et/Item/aa35e320-87b1-405b-9cac-3b90c51867d1

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